Cadence Delivers Smart JasperGold Formal Verification Platform - GADGETS & INNOVATIONS


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Wednesday, May 8, 2019

Cadence Delivers Smart JasperGold Formal Verification Platform

·  Third-generation formal verification technology delivers an average of 2X faster proofs out of the box and 5X faster regression runs by leveraging new machine learning-enabled Smart Proof Technology 
· New platform also delivers more than 2X design compilation capacity and an average of 50% memory usage reduction  

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the third-generation Cadence® JasperGold® Formal Verification Platform, featuring machine learning technology and core formal technology enhancements. The updates to the platform address the capacity and complexity challenges of today's advanced SoC designs and aim to improve verification throughput.

Smart Proof Technology
The new JasperGold platform represents the latest stage of ongoing proof-solver algorithm and orchestration improvements. This latest platform incorporates Smart Proof Technology to improve verification throughput for all JasperGold apps. Machine learning is used to select and parameterize solvers to enable faster first-time proofs. 

Additionally, machine learning is used to optimize successive runs for regression testing, either on premises or in the cloud. With Smart Proof Technology, proofs speed up by up to 4X, and up to 6X on regression runs.

Advanced Design Scalability
Given today's larger and more complex SoC designs, the design compilation process sets the maximum size of design, and the compute resources necessary, to start formal analysis. The updated JasperGold platform delivers more than 2X design compilation capacity with an average of 50% reduction in memory usage during compilation, compared with one year ago. 

Additionally, engineers can effectively scale design capacity through advanced parallel compilation technologies that optimally use available compute resources, and by running proofs on the Cloud.

Formal Signoff Enhancements
The platform's new formal coverage technologies let engineers perform IP signoff purely within the JasperGold platform. These new formal signoff technologies include improved proof-core accuracy, new techniques to derive meaningful coverage from deep bug hunting and new formal coverage analysis views. Together those features deliver signoff-quality formal coverage metrics and enable multi-engine chip-level verification closure.

The JasperGold Formal Verification Platform, part of the Cadence Verification Suite, offers comprehensive coverage in the vManager™ Metric-Driven Signoff Platform, which combines JasperGold formal results with Xcelium™ simulation and Palladium® emulation metrics to speed overall verification closure. It supports the company's System Design Enablement strategy, which enables systems and semiconductor companies to create complete, differentiated end products more efficiently.

The Cadence Verification Suite is comprised of the best-in-class JasperGold, Xcelium, Palladium and Protium™ core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

For more information on the new JasperGold Formal Verification Platform, visit

BANGALORE and SAN JOSE, California, May 8, 2019

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